This invention relates to the method of fabricating semiconductor memories, and more particularly to fabrication techniques for the charge coupled RAM cell and the double level poly-RAM cell.
During the past several years, much time and effort has gone into the development of high density, low cost memories. This is due to the computer industry's continual demand for more storage capacity at a reduced cost. As a result of past memory development work, the number of bits of storage per chip has increased from 16 to 64,000. In addition, the cost per bit has been decreased by a factor of at least 200.
A major reason for this progress has been the development of small, reliable memory cells. Thousands of these cells are formed on a single chip and the chips are interconnected to form large memories. The cost in the production of semiconductor chips is such that most of the expense is in bonding, packaging, testing, handling and the like, rather than in the cost of the small chip of silicon which contains the actual circuitry. Thus, any circuit which can be contained within a chip of a given size, for example, 30,000 square mils, will cost about the same as any other. By forming large numbers of memory cells in a chip, large economies in the cost per chip can result if reasonable yields are obtained. However, as the size of a chip increases, the yield decreases; so that the advantages of larger chip sizes are outweighed by reduction in yield. Accordingly, it is desirable to reduce the area occupied by each cell in a RAM.
Three types of cells are currently used in the construction of semiconductor random access memory chips. These memory cell types are called the one-transistor cell, the double level polysilicon cell (DLP cell), and the charge coupled cell (CC cell). Since the fabrication techniques herein disclosed relate primarily to CC cells and DLP cells the following discussion will concentrate on these two areas. The double level polysilicon cell is described in U.S. Pat. No. 3,720,922 by W. F. Kosonocky and in co-pending application, Ser. No. 648,594, filed Jan. 12, 1976, entitled "MOS Memory Cell Using Double Level Polysilicon" by Ching-Kiang Kuo. In a DLP cell two levels of polycrystalline silicon rather than one is used. The first level provides the upper plate of storage capacitors for the cells in a column. This level is connected to a bias voltage supply and is common to all cells in a column. The second level provides the gates of the MOS transistors, and also the connection from the gates to the overlying middle strip which is the X address line.
The CC cell is described in co-pending application, Ser. No. 739,758, filed Nov. 8, 1976, now issued as U.S. Pat. No. 4,060,738 on Nov. 29, 1977. The charge coupled RAM cell combines the storage capacitor and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. Two approaches have been used in making a charge coupled RAM cell, first having an implanted transfer region and second having an implanted storage region. In an N-channel CC RAM cell with an implanted storage region, the structure consists of a single gate which overlies two different gate regions. The storage region contains a shallow N-type ion implant very near the silicon oxide-silicon substrate interface and a relatively deep P-type ion implant, while the transfer region is free of implants. In the store mode, the word line gate is off, but an isolated potential well exists in the storage region due to the N-type implant which shifts the flat-band voltage to a negative value. When the word line gate is turned on, as for example in a read or write mode, the surface potential in a transfer region is more positive than that in the storage region due to the P-type implant which effectively increases the substrate doping in the storage region. The operation of this cell follows that of a one-transistor cell. The second approach that may be used to realize a CC RAM cell is a structure having an implanted transfer region where the cell has a single gate overlying a uniformly thick oxide. The storage region consists of the normal substrate material while the transfer region contains a relatively deep P-type implant to enhance the substrate doping. This implant causes the surface potential in the transfer region to vary sublinearly with gate voltage. The operation of this cell is such that when the word line is turned on to write information into the cell, a potential well is formed under the storage region whereas a barrier exists in the transfer region. If the bit line is held more positive than the surface potential in the transfer region, no charge flows and a `0` is written. If the bit line voltage is lowered below the surface potential in the transfer region, charge fills the well and a `1` is written. The word line voltage is then lowered to an intermediate level for the store mode to isolate the bit line from the storage region. To read the contents of the cell, the word line voltage is dropped to or near ground pushing the stored charge onto the bit line. The operation of this cell is a departure from that of the conventional one-transistor cell.
In the fabrication of integrated circuits there is a continuous thrust toward greater packing density. This, of course, lends itself to smaller and smaller lithographic dimensions. As the dimensions of the geometry that must be patterned decrease, the yield can be expected to decrease due to the increased difficulty in patterning the smaller geometry. With today's manufacturing equipment, alignment accuracy is greater than the minimum geometry that can be patterned, especially in optical lithography. That is, a typical align and expose tower is capable of alignment within 0.05 mils and a minimum resist definition within 0.15 or 0.20 mils in a manufacturing environment. Advantage may be taken of the alignment accuracy by employing offset alignment techniques to increase density while maintaining the same minimum patterned geometry constraint. Offset alignment fabrication techniques have been utilized in increasing the packing density in serial memory charge coupled devices as described in co-pending application, Ser. No. 691,656 filed on June 1, 1976, now issued as U.S. Pat. No. 4,027,381 on June 7, 1977, and in the publication by R. W. Bower, T. A. Zimmerman and A. M. Mohsen, entitled "A High Density Overlapping Gate Charge Coupled Device Array" presented at the IEDM, December, 1973. The present invention uses offset alignment techniques to optimize the packing density of random access memories without decreasing the minimum pattern resist geometry needed for a charge coupled cell of a double-level poly cell.